Area Optimization of Timing Resilient Designs Using Resynthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2018)
摘要
Timing resilient designs can remove variation margins by adding error detecting logic (EDL) that detects timing errors when execution completes within a resiliency window. Speeding up near-critical-paths during logic synthesis can reduce the amount of EDL needed but at the cost of increasing logic area. This creates a logic optimization strategy called resynthesis. This paper proposes four alterna...
更多查看译文
关键词
Latches,Logic gates,Clocks,Optimization,Delays,Libraries
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络