NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization.

IEEE Transactions on Circuits and Systems I: Regular Papers(2018)

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摘要
Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bun...
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关键词
Logic gates,Optimization,Tools,Delays,Clocks,Wires,Protocols
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