WB-trees: a meshed tree representation for FinFET analog layout designs

Yu-Sheng Lu
Yu-Sheng Lu
Yu-Hsuan Chang
Yu-Hsuan Chang

DAC, pp. 9:1-9:6, 2018.

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Abstract:

The emerging design requirements with the FinFET technology, along with traditional geometrical constraints, make the FinFET-based analog placement even more challenging. Previous works can handle only partial FinFET-induced design constraints because some new constraints are intrinsically different from the traditional ones; as a result,...More

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