Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems

2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC)(2018)

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Abstract
DRAM memory access is a critical performance bottleneck. To access one cache block, an entire row needs to be sensed and amplified, data restored into the bitcells and the bitlines precharged, incurring high latency. Isolating the bitlines and sense amplifiers after activation enables reads and precharges to happen in parallel. However, there are challenges in achieving this isolation. We tackle these challenges and propose an effective scheme, simultaneous read and precharge (SRP), to isolate the sense amplifiers and bitlines and serve reads and precharges in parallel. Our detailed architecture and circuit simulations demonstrate that our simultaneous read and precharge (SRP) mechanism is able to achieve an 8.6% performance benefit over baseline, while reducing sense amplifier idle power by 30%, as compared to prior work, over a wide range of workloads.
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Key words
SRP,open DRAM,high performance,DRAM memory systems,DRAM memory access,critical performance bottleneck,access one cache block,sense amplifiers,isolation,circuit simulations,simultaneous read and precharge mechanism,amplifier idle power
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