An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes

IEEE Transactions on Emerging Topics in Computing, pp. 172-183, 2018.

Cited by: 6|Views10


With the aggressive downscaling of process technologies and the importance of batterypowered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET dev...More



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