A DfT Insertion Methodology to Scannable Q-Flop Elements.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2018)
摘要
The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing autom...
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关键词
Standards,Tools,Synchronization,Protocols,Computer architecture,MOSFET,Logic gates
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