Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment

System control and the collection of analog signals are fundamental tasks in many embedded computer systems such as are found in automotive, communication, and sensor network domains. Often latency is critical and FPGAs are an attractive alternative. Traditionally, external ADC (analog to digital converter) chips have been used for analog to digital signal conversion and transfer of the digital signals to the FPGA(s). In large-scale quantum system experiments, the implementation of this classic control infrastructure is a challenge. In particular, the FPGA-based control system must work in a liquid helium environment at about 4°K. To improve the system's reliability, we need to integrate multiple lanes of soft core ADC directly into the FPGA. In this paper we propose a method of building high-speed ADCs with time to digital converters (TDCs). The experimental results show that the ADCs can achieve a sampling rate of 100Msa/s with a 6-bit resolution for signals ranging from 0 to 3 V. In our design the ADC uses primarily the ISERDES logic of a Xilinx FPGA plus a small number of CLBs. Our design can integrate 24 lanes of soft-core ADCs into a Xilinx XC7A100t-2csg324 FPGA.