Designing Soft-Error-Aware Circuits With Power And Speed Optimization

Even though power consumption for ICs has emerged as the most constraining aspect, it is important to deliver circuit designs that also meet area, speed, and soft-error rates (SER) specifications. D flip-flop (DFF) designs with different threshold voltages are fabricated at the 14/16-nm bulk FinFET CMOS technology node and evaluated for speed and SER from a power (operating parameters) perspective. The results are used to create a model that will allow designers to identify optimum design and operating parameters to meet multiple design constraints.