45nm PD SOI FET gate resistance optimization for mmw applications

This paper investigates the impact of phosphorous polysilicon gate pre-doping and silicide thickness on the gate resistance of NFETs. The analysis is performed on a 45nm partially depleted (PD) Silicon-on-Insulator (SOI) technology with a Ni silicided poly SiON gate stack. It is shown that both process features contribute differently to R g improvements, making their respective benefits dependent on device finger width (W f ). The data also show that combining both approaches can simultaneously improve R g and, consequently, device maximum oscillation frequency (F max ) on both small and large W f devices.