Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

international electron devices meeting, 2015.

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Abstract:

A CSE (charge storage efficiency) model is proposed to explain the origin of ISPP slope degradation for various charge-trapping NAND Flash devices. Experimentally it is often observed that the programming window is generally degraded as device dimension scales [1], suggesting a strong size effect. Through our model analysis, it is clarifi...More

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