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Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

IEEE Transactions on Electron Devices, no. 3 (2016): 1047-1053

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In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The firs...更多

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作者
Teng-Hao Elton Yeh
Teng-Hao Elton Yeh
Tzu-Hsuan Bruce Hsu
Tzu-Hsuan Bruce Hsu
Pei-Ying Penny Du
Pei-Ying Penny Du
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