Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND
IEEE Transactions on Electron Devices, pp. 1047-1053, 2016.
ProgrammingArraysElectric potentialLogic gatesCouplingsMore(1+)
In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The firs...More
Full Text (Upload PDF)
PPT (Upload PPT)