Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Teng-Hao Elton Yeh,Wei-Chen Chen,Tzu-Hsuan Bruce Hsu,Pei-Ying Penny Du,Chih-Chang Hsieh,Hang-Ting Lue,Yen-Hao Shih,Ya-Chin King,Chih-Yuan Lu

IEEE Transactions on Electron Devices（2016）

引用 6|浏览40

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摘要

In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges ...

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关键词

Programming,Arrays,Electric potential,Logic gates,Couplings,Algorithm design and analysis

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