CD bias control on hole pattern

Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line& space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch-litho-etch (LELE)[2][3][5]. On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. Especially roughness and X-Y CD bias are paid attention because it cause cut error and pattern defect. In this case, we applied some smoothing process to care hole roughness[4]. Each smoothing process showed different effect on X-Y CD bias. In this paper, we will report the pattern controllability comparison of trench and block + inverse. It include X-Y CD bias, roughness and process usability. Furthermore we will discuss optimum method focused on X-Y CD bias when we use additional process such as smoothing and shrink etching.