Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through-Silicon Vias: Part II

IEEE Transactions on Electron Devices, pp. 2510-2516, 2016.

Cited by: 0|Bibtex|Views2|DOI:https://doi.org/10.1109/TED.2016.2556693
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Abstract:

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number...More

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