A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

Christopher P. Miller
Christopher P. Miller
Chia-Jung Chen
Chia-Jung Chen
Scott C. Lewis
Scott C. Lewis
Jack Morrish
Jack Morrish
Tony Perri
Tony Perri
Richard Jordan
Richard Jordan
Hsin-Yi Ho
Hsin-Yi Ho
Tu-Shun Chen
Tu-Shun Chen
W.C. Chien
W.C. Chien
Mark Drapa
Mark Drapa
Tom Maffitt
Tom Maffitt

international memory workshop, pp. 1-5, 2016.

Cited by: 0|Bibtex|Views7|DOI:https://doi.org/10.1109/IMW.2016.7493563
Other Links: academic.microsoft.com

Abstract:

For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, ...More

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