Performance modeling and optimization for on-chip interconnects in STT-MRAM memory arrays
international interconnect technology conference, pp. 53-55, 2016.
This paper presents a comprehensive analysis on the limits interconnects impose on the performance, power dissipation, and lifetime of Spin-Transfer-Torque (STT) memory chips. Various approaches and memory architectures are investigated to minimize the interconnect delay and the total memory latency. In addition, the reliability challenge...More
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