Performance modeling and optimization for on-chip interconnects in STT-MRAM memory arrays

international interconnect technology conference, pp. 53-55, 2016.

Cited by: 0|Bibtex|Views4|DOI:https://doi.org/10.1109/IITC-AMC.2016.7507678
Other Links: academic.microsoft.com

Abstract:

This paper presents a comprehensive analysis on the limits interconnects impose on the performance, power dissipation, and lifetime of Spin-Transfer-Torque (STT) memory chips. Various approaches and memory architectures are investigated to minimize the interconnect delay and the total memory latency. In addition, the reliability challenge...More

Code:

Data:

Your rating :
0

 

Tags
Comments