Vertical Slit FET at 7-nm Node and Beyond

This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential f...