Pfscl Based Linear Feedback Shift Register

A new design of Linear Feedback Shift Register (LFSR) based on Positive Feedback Source Coupled Logic (PFSCL) style is presented. Four different architectures are proposed which use combination of two PFSCL based topologies (NOR based and triple-tail cell based). The theoretical proposition is verified through SPICE simulations using 0.18 mu m TSMC CMOS technology parameters. The performance of the proposed architectures is compared on the basis of delay, power consumption and power-delay product. It is found that triple-tail cell based architecture outperformed other architectures in terms of delay, power consumption by 40.3 % and 89.74 % respectively.