Modeling Interconnect Variability at Advanced Technology Nodes and Potential Solutions

Divya Prasad
Divya Prasad

IEEE Transactions on Electron Devices, pp. 1246-1253, 2017.

Cited by: 0|Bibtex|Views3|DOI:https://doi.org/10.1109/TED.2016.2645448
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Abstract:

The advent of multigate transistor technology for 20-nm technology node and beyond, has increased the importance of wire parasitics, in particular, wire resistance in determining the circuit delay computation. Variability in wire dimensions directly impacts the wire parasitics, hence, the overall system performance. For the first time, in...More

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