Reliability characterization of 10nm FinFET technology with multi-VT gate stack for low power and high performance

Minjung Jin,Changze Liu,Jinju Kim,Jungin Kim,Hyewon Shim,Kangjung Kim,Gunrae Kim,Soonyoung Lee,Taiki Uemura, Man Chang, Taehyun An,Junekyun Park,Sangwoo Pae

2016 IEEE International Electron Devices Meeting (IEDM)（2016）

引用 29|浏览15

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摘要

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-V _T 's through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different V _T -types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

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关键词

reliability characterization,multiVT gate stack,low power performance,FinFET process technology,work function engineering,BTI,fin shape,transistor self-heating,PMOS HCI enhancement,on-state TDDB,AC mode operations,SRAM,SER,size 10 nm

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