Reduction of wafer arcing during high aspect ratio etching

international convention on information and communication technology electronics and microelectronics, pp. 421-425, 2017.

Cited by: 0|Bibtex|Views20|DOI:https://doi.org/10.23919/MIPRO.2017.7966620
Other Links: academic.microsoft.com

Abstract:

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.

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