A circuit simulation flow for substrate minority carrier injection in smart power ICs

This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.