Device And Process Design Of Leading Edge Transistors For Performance And Yield

Hans-Joachim L. Gossmann, Steven S. Sherman,Morgan Evans, Kevin Anglin

2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)（2016）

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摘要

The three-dimensional (3D) nature and continued dimensional scaling of Fin-, Nanowire-, and Gate-All-Around-FETs raise a host of unique challenges to device and process design that impact both performance and yield. We highlight selected technology challenges and solutions, specifically doping requirements for isolation, SD/E, and contact, as well as a new advanced planarization technique.

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关键词

edge transistors,3D nature,three-dimensional nature,gate-all-around-FET,nanowire FET,FinFET

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