FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane
San Francisco, CA, USA（1994）
摘要
Recent parallel processor supercomputer designs use an active backplane of routers to form the interconnections between processing elements. Today, high-bandwidth interconnect systems capable of scaling to configurations with more than 500 processing nodes tend to use self-timed designs. This avoids clock distribution problems seen in large phase-sensitive synchronous systems. The BiCMOS routing component described in this paper employs 200 MHz clocked communication for large scalable parallel-processor supercomputer systems. This scheme eliminates need for clock edges to be phase-aligned across the clock distribution network. Additionally, router inputs accept data at any phase relationship to the receiving router internal clock.<>
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关键词
bicmos integrated circuits,clocks,data communication equipment,multiprocessor interconnection networks,network routing,parallel machines,system buses,200 mhz,3.8 gb/s,bicmos routing component,fa 18.4,active backplane,clock distribution problems,clock edges,clocked communication,high-bandwidth interconnect systems,multiprocessor supercomputer backplane,phase relationship,phase-tolerant data-communication router,processing element interconnections,processor configurations,receiving router internal clock,scalable parallel processor,scaling,self-timed designs
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