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Replacing global wires with an on-chip network: a power analysis
international symposium on low power electronics and design, pp.369-374, (2005)
EI
Abstract
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and voltage scaling, to significantly reduce the energy to send a bit across chip. We develop an analytic model of large chip designs with an on-chip two-dimensional mes...More
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