A comparison of asynchronous QDI templates using static logic

Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. The literature proposes several QDI design templates with different trade-offs, giving designers a large spectrum of options to use, adapt or even mix. Among these, NULL Convention Logic (NCL), NCL+, Autonomous Signal-Validity Half-Buffer (ASVHB) and Sleep Convention Logic (SCL) are potential alternatives for low and ultra-low power applications. This paper evaluates these four QDI templates through an 8-bit Kogge-Stone full adder case study, showing analysis on cycle time, energy per operation, leakage power, energy-delay product (EDP), leakage-delay product (LDP) and area consumption. It also qualitatively evaluates each template, pointing out specific characteristics that can be suitable for low power applications.