A Comprehensive Evaluation of the Performance of Fin-type Epitaxial Tunnel Layer (ETL) Tunnel FET

Epitaxial tunnel layer tunnel FET (ETL TFET) is one of the promising device for ultra-low power applications. In this work, device performance between planar ETL TFET and Fin ETL TFET are evaluated. For n-type TFET, the electric field enhancement in Si region due to the fin structure results in Si-to-Ge and Si-to-Si tunneling at low voltage so that the subthreshold swing is degraded. For the p-type TFET, different TFET structures show similar subthreshold swing because only Ge-to-Ge tunneling occurs. In comparison with the planar TFET, Fin TFET exhibits 35% improvement and 40% degradation on conduction current for n-type and p-type TFET, respectively.