New Mixed-Mode Design Methodology for High-Efficiency Outphasing Chireix Amplifiers

A new design methodology providing optimal mixed-mode operation for dual-input class-F outphasing Chireix amplifiers is presented. The design starts with single-transistor class-F simulations at the intrinsic $I$ – $V$ reference planes to directly select the optimal peak and backoff resistive loads ${R}_{\mathrm{min}}$ and ${R}_{\mathrm{max}}$ and input RF gate drives yielding the best combination of efficiencies and output powers without needing to perform a load pull simulation or measurement. New analytic equations expressed only in terms of ${R}_{\mathrm{min}}$ and ${R}_{\mathrm{max}}$ are given for designing the Chireix combiner at the current source reference planes. Nonlinear embedding is then used to predict the incident power and multi-harmonic source and load impedances required at the package reference planes to physically implement the power amplifier (PA). An analytic formula solely expressed in terms of ${R}_{\mathrm{min}}$ and ${R}_{\mathrm{max}}$ is reported for the peak and backoff outphasing angles required at the PA input reference planes. A Chireix outphasing PA is designed using two 15-W GaN HEMTs. A Chireix outphasing PA exhibits a peak efficiency of 72.58% with peak power of 43.97 dBm and a 8-dB backoff efficiency of 75.22% at 1.9 GHz. Measurements with 10-MHz LTE signals with 9.6-dB PAPR yield 59.4% average drain efficiency at 1.9 GHz while satisfying the 3GPP linearity requirements.