A physics-based Quasi-2D model to understand the wordline (WL) interference effects of junction-free structure of 3D NAND and experimental study in a 3D NAND flash test chip

international electron devices meeting, 2017.

Cited by: 1|Bibtex|Views15|

Abstract:

3D NAND is usually designed with the charge-trapping (CT) device, arranged in a “junction-free” structure where the transistors are serially connected without a N+ diffusion junction in between them. This paper provides a physics-based quasi-2D model and several analytical equations that can readily simulate the surface potential variatio...More

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