A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL

Nowadays science has made great progress in extracting information from DNA and the huge amounts of data that is being produced need new ways and architectures to carry on the computation in an efficient way. Among the different analysis performed on the DNA, one of the most compute intensive concerns the task of aligning a set of strings (reads) to specific targets. In these regards, Lawrence Berkeley National Laboratory (LBNL) and the University of California Berkeley (UCB) developed the merAligner: a fully parallel sequence aligner that uses a seed-and-extend algorithm to perform the alignment. This aligner is able to scale up efficiently to thousands of cores on a Cray XC30 supercomputer. Despite the high computational power, this architecture consumes a significant amount of power, reducing considerably its power efficiency. To this end, reconfigurable hardware architectures have demonstrated to be able to deliver high performances, while keeping a relatively low power profile. In this work, we propose an FPGA architecture for the alignment step of the merAligner. The architecture has been designed using Chisel HCL, while the final architecture has been synthesized using Xilinx SDAccel targeting a Xilinx Kintex Ultrascale board. Final results are capable of outperforming merAligner alignment step on a test dataset by a factor of up to 7x in performance and 66x in power efficiency.