2 × 3.2 Gb/s single-ended IO transmitter with low-power dynamic FIR driver for the LPDDR4 standard

A novel FIR driver that can be applied to a low power mode in the (Low Power Double Data Rate 4) LPDDR4 standard has been developed. The proto-type transmitter architecture is implemented in 45 nm CMOS process and occupies 0.009 mm2 area. The pre-emphasis tap weighting improves the eye opening by 27.9% vertically and 27% horizontally, respectively, and the transmitter consumes only 2.25 mW at 3.2 ...