Process Optimization Of Perpendicular Magnetic Tunnel Junction Arrays For Last-Level Cache Beyond 7 Nm Node

This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm.mu m(2), H-SAF similar to 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10(-6) write error rate was reached at 0.4 pJ, V-BD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400 degrees C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.