Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms
IEEE Transactions on Electron Devices(2018)
摘要
In this paper, compact circuit models and HSPICE simulations are used to benchmark die-to-die communication channels in 2.5-D and 3-D heterogeneous integration platforms. The delay, energy-per-bit, and bandwidth-density of the considered integration platforms are simulated and benchmarked. Compared to other 2.5-D integrated systems with a 1-mm interconnect length, heterogeneous interconnect stitch...
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关键词
Wires,Integrated circuit interconnections,Benchmark testing,Integrated circuit modeling,Solid modeling,Through-silicon vias
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