Yield Modeling and Analysis of Bundled Data and Ring-Oscillator Based Designs

Huimei Cheng
Huimei Cheng
Haipeng Zha
Haipeng Zha

IET Computers & Digital Techniques, pp. 262-272, 2019.

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Abstract:

The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mat...More

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