A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)(2019)

引用 0|浏览34
暂无评分
摘要
This paper presents the results of the first ASIC implementation of the authenticated encryption scheme KetjeSR. The design covers the encryption and decryption operation in combination with a handshake protocol for the data transfer. The chip implementation was done in a TSMC 90nm GUTM process. The encryption/decryption module has an area footprint of 12.2kGE. The processor reaches an end-to-end throughput of 2.08 Gbps when running at a clock frequency of 130 MHz. The design was further optimized for low power and consumes 2.421 mW. The optimization is based on the reuse of the permutation function in combination with extensive pipelining. In terms of energy, the encryption operation costs 1.16 pJ/bit.
更多
查看译文
关键词
decryption operation,chip implementation,encryption operation costs,authenticated encryption scheme KetjeSR,ASIC implementation,encryption-decryption module,TSMC GUTM process,lightweight processor,handshake protocol,data transfer,permutation function,frequency 130.0 MHz,power 2.421 mW,size 90.0 nm,bit rate 2.08 Gbit/s
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要