A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET

A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential signaling is employed, using only a continuous time linear equalizer (CTLE) in the receiver to perform equalization. The transceiver incorporates low swing signaling, a central PLL with regulated CMOS clock distribution, and an injection-locked oscillator (ILO)-based per-lane skew adjustment. At the system level, a common reference clock is used to increase link margin through jitter tracking. The transceiver achieves a BER of <;1e-15 over a channel with 8dB loss at 28GHz with an efficiency of 2.25pJ/bit.