CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems

A new computing architecture, an annealing machine, which is specialized to solve combinatorial optimization problems, is proposed. The annealing machine maps optimization problems to an Ising model and solves the optimization problems by its own convergence property. We proposed a CMOS implementation of the annealing machine, which is a type of an in-memory computing. We constructed two prototypes of the CMOS annealing machine. The 1st-generation prototype confirmed the power efficiency is 1800times higher than that of the conventional von-Neumann computers. The FPGA 2md-generation prototype is used to explore its applications and is also confirmed its multiple-chip operation.