A Virtual Image Accelerator for Graph Cuts Inference on FPGA

Graph Cuts is a popular technique for Maximum A Posteriori inference in computer vision. It transforms a Markov Random Field problem into a network flow problem, solved via the Push-Relabel algorithm. While attractively simple, the large size of a typical image and the large number of necessary pixel-level iterations render the technique computationally expensive. Prior accelerator attempts have been reported with GPUs and FPGAs. In 2017, we demonstrated the first pixel-parallel architecture on FPGA, but limited to only 256-pixel images. This paper extends this pixel-parallel concept and proposed a Virtual-Image architecture which solves the size limitation. We demonstrate the first working virtual-image Graph Cuts accelerator, implemented on a state of the art FPGA, applied to standard benchmark images for a background segmentation task. The design is 11-13× faster than other FPGA designs, and slightly faster than a modern GPU benchmark by about 30%.