Superb Endurance and Appropriate Vth of PCM Pillar Cell using Buffer Layer for 3D Cross-Point Memory

A reliability study for phase change memory (PCM) pillar cell is performed. We found that without a buffer layer, the PCM pillar cell shows earlier endurance failure than its mushroom counterpart, and the underlying failure mechanism is attributed to element segregation. A buffer layer between PCM and top electrode is found to substantially improve the endurance characteristics of the PCM pillar cell to greater than 1E10 program cycles. In addition, the buffer layer also provides the benefit of increased PCM threshold voltage (Vth), which can enlarge the read window margin for the OTS+PCM 3D Cross-Point Memory array.