A Terabit Readout System For The Lhcb Velo Upgrade I

This paper will describe the high-speed readout challenge for the new pixel vertex detector (VELO) of the upgraded LHCb experiment, scheduled for installation in 2019/2020. All elements of the electronics readout chain will be upgraded to cope with the requirement of similar to 40 MHz full event readout rate. The pixel sensors are equipped with VeloPix ASICs and placed at similar to 5 mm from the beam in a secondary vacuum tank and extremely high and nonhomogeneous radiation environment. The highest occupancy front-end ASICs will have pixel-hit rates above similar to 800 Mhits/s using four 5.13 Gbits/s data links. Each module houses six VeloPix ASICs, wire bonded to two front-end hybrids. These are connected via very low mass kapton tapes to a control hybrid hosting one GBTx ASIC with one 4.8 Gbits/s bidirectional link. High speed signals are transmitted to the wall of the vacuum chamber using low mass flex tapes. A custom board routes the signals outside the vacuum tank and once on the air side, an Optical and Power Board converts the electrical high speed signals into optical signals for transmission from the cavern to the off-detector electronics.