FPGA Demonstration of Adaptive Low-latency High-fidelity Analog-to-digital Compression for Beyond-5G Wireless-wired Conversion

Time-domain analog-to-digital compression (ADX) is designed and implemented on FPGA for low-complexity high-fidelity wireless-wired signal conversion. We demonstrate 50ns processing latency and $EVM < 0.6\%\ over > 30dB$ input power range for 4096QAM-modulated OFDM and single-carrier radio signals.