Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction - work-in-progress

Ruben Vazquez
Ruben Vazquez

CODES+ISSS, pp. 1-2, 2019.

Cited by: 0|Bibtex|Views1|DOI:https://doi.org/10.1145/3349567.3351730
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Other Links: dblp.uni-trier.de|academic.microsoft.com|dl.acm.org

Abstract:

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.

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