Energy-Efficient Differential Spin Hall MRAM-Based 4-2 Magnetic Compressor

The compressors are widely used as bit compressing cells having key applications with multi-operand addition and multiplication hardware. As the CMOS technology scales down below 45 nm technology nodes, static power dissipation becomes a major concern. To overcome this constraint, spin transfer torque magnetic random access memory (STT-MRAM)-based hybrid CMOS/MTJ architectures are being used. Inception of perpendicular magnetic tunnel junction (PMTJ) has enhanced the growth of spintronics-based hybrid architectures, due to their low switching current, scalability, non-volatility, and CMOS compatibility. Recently, a large number of circuits based on STT-MRAM have been proposed. However, they have limitations related to reliability and high write energy. In this article, we propose a differential spin Hall MRAM (DSH-MRAM)-based hybrid CMOS/MTJ magnetic 4-2 compressor. A write voltage of 0.4 V and 300 ps current pulse are used to switch the magnetization state of the MTJs. When compared with previous STT-MRAM-based designs, the proposed compressor shows 97% improvement in power-delay product (PDP) characteristics. The write circuit in DSH-MRAM consumes merely 5 nW in comparison to 2 mu W by conventional STT-MRAM designs. Moreover, the narrow write pulse promotes the proposed design for input frequencies up to 1 GHz.