Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme
IEEE Transactions on Electron Devices(2020)
摘要
In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL suffer is appreciably alleviated. The second scheme takes advantage of a unique behavior termed “self-boosting-enhanced-PGM” mechanism in the pair- bitline PGM method to deal with the slow PGM bits and achieve a much lower bit error rate as a consequence. By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82%.
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关键词
Computer architecture,Microprocessors,Flash memories,Erbium,Hot carrier effects,Logic gates,Bit error rate
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