Seiba - An FPGA Overlay-Based Approach to Rapid Application Development
ReConFig, pp. 1-8, 2019.
Although high-level synthesis (HLS) improves designer productivity through abstraction, FPGA high-level synthesis stills suffers from lengthy compilation that limits the number of design iterations a developer can achieve per day. One method of minimizing these compile times is compiling designs with innate programmability, aka FPGA overl...More
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