An Empirically Validated Virtual Source Fet Model For Deeply Scaled Cool Cmos
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2019）
摘要
In this work we extend the compact Virtual Source (VS) model for nanoscale MOSFET from room temperature to 6K to advance the development of an ultra-compact model for low temperature CMOS (Cool-CMOS) technology. To achieve this we characterize 30 nm channel length bulk-Si CMOS FETs from 300K to 6K and extract the VS model parameters to investigate the ballistic efficiency of nanoscale FETs as a function of temperature. We conclude that while ballistic efficiency of nanoscale MOSFETs degrade in linear region as we approach cryogenic temperature, its ballistic efficiency improves in the saturation region at low temperature. Parametric VDD sweeps show that the VS model is also ready for use in low power cryogenic circuit design. Finally, the model is used to project performance of Cool CMOS technology for 15nm channel length FETs at deeply scaled nodes and prove its viability for use.
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关键词
VS model,parametric voltage sweeps,saturation region,low temperature CMOS technology,deeply scaled cool CMOS technology,virtual source FET model,channel length bulk-silicon CMOS FETs,deeply scaled nodes,low power cryogenic circuit design,cryogenic temperature,nanoscale MOSFETs,nanoscale FETs,ballistic efficiency,ultra-compact model,room temperature,nanoscale MOSFET,compact virtual source model,size 30.0 nm,size 15.0 nm,temperature 300 K to 6 K,Si
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