Fluctuating Power Logic: SCA Protection by $V_{DD}$ Randomization at the Cell-level

In this paper, we propose a novel cell-level side channel countermeasure fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic. The countermeasure further acts as a cell-level V DD randomizer, making it a strong candidate for implementing algorithmic countermeasure and exploiting its noise generation capabilities. This proposed scheme is illustrated by a standard flip-flop. HSPICE based simulation results show that the modified flip-flop is resistant against power analysis at the cost of doubled power dissipation. Two illustrative case studies of PRESENT and AES substitutions have been explored. The resistance against Side-Channel Analysis(SCA) is evaluated by the correlation power analysis. The new logic outperforms other counterparts in consideration of both security and cost, which renders it as a practical solution for resource-constrained systems. The proposed cell-level countermeasure can naturally mitigate other SCA such as electromagnetic analysis.