A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory
ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK Pittsburgh Pennsylvania October, 2016, pp. 1-10, 2016.
The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also results in severe disturbance problems. In this work, we propose to create sub-blocks i...More
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