A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Brian Zimmer,Rangharajan Venkatesan,Yakun Sophia Shao,Jason Clemons,Matthew Fojtik,Nan Jiang,Ben Keller,Alicia Klinefelter,Nathaniel Ross Pinckney,Priyanka Raina,Stephen G. Tell,Yanqing Zhang,William J. Dally,Joel S. Emer,C. Thomas Gray,Stephen W. Keckler,Brucek Khailany

IEEE Journal of Solid-State Circuits（2020）

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摘要

Custom accelerators improve the energy efficiency, area efficiency, and performance of deep neural network (DNN) inference. This article presents a scalable DNN accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic chip are optimal for specific network sizes,...

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关键词

Tensors,Neural networks,Computer architecture,System-on-chip,Prototypes,Convolution,Bandwidth

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