Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes

Sugie Yuya
Sugie Yuya
Yoshida Yuki
Yoshida Yuki
Mertig Normann
Mertig Normann
Teramoto Hiroshi
Teramoto Hiroshi
Minato Shin-ichi
Minato Shin-ichi

Soft Comput., pp. 1731-1749, 2021.

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Abstract:

Minor embedding heuristics have become an indispensable tool for compiling problems in quadratically unconstrained binary optimization (QUBO) into the hardware graphs of quantum and CMOS annealing processors. While recent embedding heuristics have been developed for annealers of moderate size (about 2000 nodes) the size of the latest CM...More

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