Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme

2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)(2019)

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摘要
Memristive devices have the potential to reduce the memory access bottleneck in conventional computer architectures. However, memristive devices also suffer from low endurance and large resistance variation. To address these problems, we present a robust logic scheme named Enhanced Scouting Logic (ESL). It produces logic operation results within the peripheral circuit of the memory array. During the execution of logic operations, the resistance states of memristive devices do not change and hence do not affect the memristor lifetime. ESL senses the resistance of input memristive devices via two different paths when different operations such as AND and OR are performed. These different paths guarantee the operation correctness even under large resistance variations. We verified ESL using SPICE simulations and Monte Carlo analysis. Our simulation results show that ESL is more robust as compared with state-of-the-art logic schemes.
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关键词
Monte Carlo analysis,SPICE simulations,peripheral circuit,memristor lifetime,input memristive devices,resistance states,logic operations,memory array,ESL,resistance variation,computer architectures,memory access bottleneck,robust memristive Logic design scheme,Enhanced Scouting Logic
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